The present invention relates to a method for fabricating a semiconductor device, more specifically, a method for fabricating a logic semiconductor device combined with a non-volatile memory.
The nonvolatile semiconductor memory cell, such as the flash memory, etc., includes a floating gate for accumulating charges in addition to a control gate for driving the transistor. The floating gate is an electrode which is electrically floating and requires no interconnection to be electrically connected thereto.
However, often an interconnection is electrically connected to a conductive layer which is simultaneously formed with and formed in the same interconnection level as the floating gate in accordance with requirements, etc. of the process control and the device structure/the fabrication process. For example, the process TEG (test element group) used in quality control, etc. of the tunnel gate insulating film includes a MOS capacitor having as the upper electrode the conductive layer formed in the same interconnection level as the floating gate. In the NAND flash memory cell, the conductive layer formed in the same interconnection level as the floating gate is often used as the gate electrode of the selective transistor.
Usually, the gate electrode of the flash memory cell of the stack gate structure has the floating gate formed of first-level polycrystalline silicon film and the control gate formed of second-level polycrystalline silicon film. The gate electrode of the peripheral transistor of the single-layer gate structure is formed of the second-level polycrystalline silicon film. Between the floating gate and the control gate, an inter-gate insulating film for insulating and capacitively coupling the electrodes with each other is formed. The inter-gate insulating film is formed typically of the layer film of silicon oxide film and silicon nitride film (e.g., ONO film) and is absent in the peripheral transistor region.
The first-level polycrystalline silicon film is processed simultaneously with the gate electrode of the flash memory cell and is covered with the inter-gate insulating film and the second-level polycrystalline silicon film. Accordingly, when an interconnection is formed in contact with the first-level polycrystalline silicon film, the inter-gate insulating film and the second-level polycrystalline silicon film formed over the first-level polycrystalline silicon film must be removed. Of these films, the second-level polycrystalline silicon film can be removed simultaneously with patterning the gate electrode of the peripheral transistor, but to remove the inter-gate insulating film, another step of removing the inter-gate insulating film is required.
As methods for removing the inter-gate insulating film formed over the first-level polycrystalline silicon film of the same level as the floating gate, the following three methods have been conventionally used.
In the first method, when a contact hole down to the silicon substrate and a contact hole down to the first-level polycrystalline silicon film are opened, the inter-gate insulating film over the first-level polycrystalline silicon film is removed.
In the second method, in the etching-back step for forming the sidewall insulating film on the side walls of the gate electrodes of the second-level polycrystalline silicon film, the inter-gate insulating film over the first-level polycrystalline silicon film is removed.
In the third method, when the second-level polycrystalline silicon film is patterned to form the gate electrode, the inter-gate insulating film over the first-level polycrystalline silicon film is removed.
The related arts are disclosed in, e.g., Reference 1 (Japanese published unexamined patent application No. 2005-123524), Reference 2 (Japanese published unexamined patent application No. 2005-311282), and Reference 3 (Japanese published unexamined patent application No. 2004-356580).
In the first method described above, the inter-gate insulating film over the first-level polycrystalline silicon film must be removed after the contact hole down to the substrate is completely opened, and the contact part of the substrate is damaged by the etching in the step of etching the inter-gate insulating film. The first method is not compatible with the borderless contact and is not applicable to the fabrication process for the flash memory cell combined with the leading logic device using the borderless contact.
The second and the third method described above require extra-etching for removing the inter-gate insulating film. According to this, characteristic changes of the peripheral transistor are often caused by the etching damages introduced into the silicon substrate and/or the film thickness decrease of the device isolation film by the etching-back step. This is serious especially when the gate insulating film of the peripheral transistor is thin. It is difficult to apply the second and the third methods to the fabrication process for the flash memory cell combined with the leading logic device.
As means for solving these problems, it is an idea to add the masking step for removing the inter-gate insulating film over the first-level polycrystalline silicon film, but unpreferably this adds to the step number and increases the fabrication cost.
As described above, it is difficult to apply the conventional methods for fabricating the flash memory cell, in which the interconnection is formed in contact with the first-level polycrystalline silicon film of the same level as the floating gate to the processing for fabricating the leading logic semiconductor device combined with the nonvolatile semiconductor memory.